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RISC-V XV6/Linux SoC, marchID: 0x2b
Updated
Nov 28, 2025
Verilog
Skywaters 130nm Klayout PDK
Updated
Jan 29, 2025
Python
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
Updated
May 9, 2022
SystemVerilog
SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.
Updated
Aug 31, 2025
SystemVerilog
An open source SoC project for the VLSI 2 class at ETHZ. Selected as one of the best design and taped out in IHP 130nm technology
Updated
Nov 16, 2025
SystemVerilog
VSDIAT Documentation- Openlane/Sky130- MIT
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